Memory cells in semiconductor memory device may cause soft error induced by radioactive ray. Most of the soft errors induced by radioactive ray, in the era of larger design rules, were found in a single bit. However, with recent shrinkage of the design rules, the soft error has become more likely to occur in a plurality of consecutive memory cells by a single shot of radioactive ray (neutron ray is particularly affective).
One general measure against the soft error is to correct errors, by externally adding ECC (Error Correcting Code) to the semiconductor memory device. The error correction is, however, difficult when errors occur at a plurality of data I/O terminals owned by the semiconductor memory device (multi-bit error), since scale of a circuit necessarily added a corrective function will be very large.
A conventional technique of suppressing the multi-bit error ever proposed is such as adopting a column configuration, and bringing physical position of the memory cells, accessible corresponding to the individual data I/O terminals in a single cycle, apart from each other. Other known techniques for DRAM circuit proposed in Japanese Laid-Open Patent Publication Nos. 2000-268560 and 2008-217916, basically adopt physical structures similar to the column structure, so as to bring the physical position of the memory cells, accessible in a single cycle, apart from each other.
For example, in a semiconductor memory device configured to have a four-column structure as illustrated in FIG. 8A, one block is formed by a group of every single COL#0, COL#1, COL#2 and COL#3, and every block is corresponded to each of I/O terminals for data D0 to D2. Correspondent memory cells in the individual blocks are accessed in a single cycle. More specifically, in a single access with a certain address, every fourth memory cell (memory cells in every fourth low) is accessed. Accordingly, even if the soft error due to radioactive ray may occur in hatched cells in FIG. 8A, the error possibly occurs in a single cycle is a one-bit error, and may be coped with the one-bit ECC.
However, in the memory cells of the semiconductor memory device having been shrunk in size under more reduced design rules, the number of memory cells possibly causing the soft error by a single shot of radioactive ray may increase. For example, if the memory cells are shrunk in size as illustrated in FIG. 8B, the semiconductor memory device may cause the soft error in a larger number of memory cells as compared with the example illustrated in FIG. 8A, even under the same four-column configuration. If the soft error due to radioactive ray occurs in the hatched memory cells as illustrated in FIG. 8B, a two-bit error possibly occurs in a single cycle (when accessed by COL#0). Correction of the two-bit error needs a two-bit ECC, but this means a very large scale of additional circuit and makes the error correction difficult.
The two-bit error described in the above may be suppressed by configuring the semiconductor memory device to have, as illustrated in FIG. 8C, the number of columns in a single row exceeding the number of memory cells possibly causing the soft error by a single shot of radioactive ray. FIG. 8C illustrates an exemplary case where an eight-column configuration was adopted while keeping the size of the memory cells in FIG. 8B unchanged. In FIG. 8C, one block is configured by a group of every single COL#0, COL#1, COL#2, COL#3, COL#4, COL#5, COL#6 and COL#7, and every block is corresponded to each of I/O terminals for data D0 to D2. According to the configuration illustrated in FIG. 8C, the error possibly occur in a single cycle of access is a one-bit error, and may be coped with one-bit ECC.
However, a problem described below would arise by the increased number of columns, as exemplified in FIG. 8C. For an exemplary case where a large number of data I/O terminals are required such as in semiconductor memory devices used for high-performance processors, it becomes more difficult to provide a necessary number of data I/O terminals, since the number of data I/O terminals mountable in the same physical size of space in the column-wise direction decreases. An effort of configuring the semiconductor memory device so as to provide the necessary number of data I/O terminals will result in an enlarged circuit area. For example, comparing FIG. 8B with FIG. 8C, the number of data I/O terminals in FIG. 8C in the same physical size of space (lateral width) is found to be half of that in FIG. 8B. If the semiconductor memory device is configured to provide the required number of data I/O terminals as illustrated in FIG. 8C, the lateral width will be doubled from that illustrated in FIG. 8B, thereby the circuit area will increase, and access time will become slower as a consequence.